AS4C128M8D3LB-12BCNTR

Alliance Memory
913-4C1288D3LB12BCNT
AS4C128M8D3LB-12BCNTR

Mfr.:

Description:
DRAM 1G 1.35V 800MHz 128Mx8 DDR3 E-Temp

ECAD Model:
Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

Availability

Stock:
Non-Stocked
Factory Lead Time:
8 Weeks Estimated factory production time.
Minimum: 2500   Multiples: 2500
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:
This Product Ships FREE

Pricing (EUR)

Qty. Unit Price
Ext. Price
Full Reel (Order in multiples of 2500)
4,57 € 11.425,00 €

Alternative Packaging

Mfr. Part No.:
Packaging:
Tray
Availability:
In Stock
Price:
7,35 €
Min:
1

Product Attribute Attribute Value Select Attribute
Alliance Memory
Product Category: DRAM
RoHS:  
SDRAM - DDR3L
1 Gbit
8 bit
800 MHz
FBGA-78
128 M x 8
225 ps
1.283 V
1.45 V
0 C
+ 95 C
AS4C128M8D3LB
Reel
Brand: Alliance Memory
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 2500
Subcategory: Memory & Data Storage
Supply Current - Max: 72 mA
Products found:
To show similar products, select at least one checkbox
Select at least one checkbox above to show similar products in this category.
Attributes selected: 0

CAHTS:
8542320020
USHTS:
8542320032
MXHTS:
8542320201
ECCN:
EAR99

DDR3 Synchronous DRAM

Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features, and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source synchronous fashion. These Alliance Memory devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface that transfers two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Alliance Memory DDR3L SDRAM is available in various package sizes.