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TMS320VC5509AZHH

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See Product Specifications

Mouser No:

595-S320VC5509AZHH

Mfr. No:

TMS320VC5509AZHH

Mfr.:

Texas Instruments

Description:

Digital Signal Processors & Controllers - DSP, DSC Fixed-Point DSP

Lifecycle:

Obsolete

Datasheet:

TMS320VC5509AZHH Datasheet

ECAD Model:

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Digital Signal Processors & Controllers - DSP, DSC
Delivery Restrictions:	Mouser does not presently sell this product in your region.
RoHS:
Product:	DSPs
Core:	C55x
Maximum Clock Frequency:	200 MHz
Package/Case:	BGA-179 Microstar
Program Memory Size:	64 kB
Data RAM Size:	128 kB
Operating Supply Voltage:	1.6 V
Series:	TMS320VC5509A
Mounting Style:	SMD/SMT
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Packaging:	Tray
Brand:	Texas Instruments
Data Bus Width:	32 bit
Development Kit:	TMDSDSK5509
I/O Voltage:	3.3 V
Instruction Type:	Fixed Point
Moisture Sensitive:	Yes
Product Type:	DSP - Digital Signal Processors & Controllers
Factory Pack Quantity:	160
Subcategory:	Embedded Processors & Controllers
Part # Aliases:	C5509ZOOME1C2103DR VC55GPSZHH
Unit Weight:	337,800 mg

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Datasheet

TMS320VC5509AZHH Datasheet

Application Notes

EOL

Images

PCN

12x12 BGA tray change (PDF)

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Compliance Codes

TARIC:: 8542319000
CNHTS:: 8542319090
CAHTS:: 8542310000
USHTS:: 8542310035
JPHTS:: 8542310335
KRHTS:: 8542311000
MXHTS:: 8542310399
ECCN:: 3A991.a.2

Origin Classifications

Country of Origin:: Philippines
Assembly Country of Origin:: Not available
Country of Diffusion:: Not available

The country is subject to change at the time of shipment.

TMS320VC5509AZHH DSP

The Texas Instruments TM320VC5509AZHH fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU core. The TI TM320VC5509A achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU of the TI TM320VC5509AZHH DSP supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity.