SN74HC393PW

595-SN74HC393PW
SN74HC393PW

Mfr.:

Description:
Counter ICs Dual 4-Bit Binary Counters

Lifecycle:
End of Life:
Scheduled for obsolescence and will be discontinued by the manufacturer.
Datasheet:
ECAD Model:
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In Stock: 1.686

Stock:
1.686 Can Dispatch Immediately
Quantities greater than 1686 will be subject to minimum order requirements.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:

Pricing (EUR)

Qty. Unit Price
Ext. Price
0,851 € 0,85 €
0,819 € 442,26 €
0,688 € 743,04 €
0,419 € 1.696,95 €
0,383 € 3.067,83 €

Alternative Packaging

Mfr. Part No.:
SN74HC393PWR
Packaging:
Reel, Cut Tape, MouseReel
Availability:
In Stock
Price:
1,17 €
Min:
1
Mfr. Part No.:
SN74HC393PWRG4
Packaging:
Reel, Cut Tape, MouseReel
Availability:
In Stock
Price:
0,85 €
Min:
1

Similar Product

Texas Instruments SN74HC393PWR
Texas Instruments
Counter ICs Dual 4-Bit Binary Co unters A 595-SN74HC A 595-SN74HC393PW
Compare With Current Part

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Counter ICs
RoHS:  
SMD/SMT
TSSOP-14
Binary
HC
4 bit
Asynchronous
2 V to 6 V
- 40 C
+ 85 C
SN74HC393
Tube
Brand: Texas Instruments
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: MY
Product Type: Counter ICs
Factory Pack Quantity: 90
Subcategory: Counter ICs
Unit Weight: 57,200 mg
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Attributes selected: 0

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TARIC:
8542399000
CNHTS:
8542319090
CAHTS:
8542390000
USHTS:
8542390090
JPHTS:
8542390990
MXHTS:
85423999
ECCN:
EAR99

SN74HC393/SN74HCS393 Dual 4-Bit Binary Counters

Texas Instruments SN74HC393/SN74HCS393 Dual 4-Bit Binary Counters contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK) input. N-bit binary counters can be implemented with each package, providing the capability of dividing by 256. The Texas Instruments SN74HC393/SN74HCS393 have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.

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