SN74AC174WBQBRQ1

Texas Instruments
595-SN74AC174WBQBRQ1
SN74AC174WBQBRQ1

Mfr.:

Description:
Flip-Flops Automotive hex D-typ e flip-flops with c

Lifecycle:
New Product:
New from this manufacturer.
ECAD Model:
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In Stock: 3.000

Stock:
3.000 Can Dispatch Immediately
Factory Lead Time:
12 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:

Pricing (EUR)

Qty. Unit Price
Ext. Price
0,559 € 0,56 €
0,393 € 3,93 €
0,353 € 8,83 €
0,308 € 30,80 €
0,287 € 71,75 €
0,274 € 137,00 €
0,269 € 269,00 €
Full Reel (Order in multiples of 3000)
0,268 € 804,00 €
0,243 € 1.458,00 €

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Flip-Flops
RoHS:  
D-Type
SN74
1 Circuit
Push-Pull
WQFN-16
CMOS
Positive
- 24 mA
24 mA
1.5 V
5.5 V
SMD/SMT
- 40 C
+ 125 C
Reel
Cut Tape
Brand: Texas Instruments
Maximum Clock Frequency: 150 MHz
Number of Input Lines: 3 Line
Number of Output Lines: 1 Line
Product Type: Flip Flops
Series: SN74AC174
Factory Pack Quantity: 3000
Subcategory: Logic ICs
Triggering Type: Positive Edge
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Attributes selected: 0

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TARIC:
8542319000
USHTS:
8542390090
MXHTS:
8542399999
ECCN:
EAR99

SN74AC174-Q1 Hex D-Type Flip-Flops

Texas Instruments SN74AC174-Q1 Hex D-Type Flip-Flops contain six D-type flip-flops with shared active-low clear (CLR) and rising-edge triggered (CLK) inputs. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input does not affect the output. Texas Instruments SN74AC174-Q1 devices are AEC-Q100 qualified for automotive applications.

SN74ACT164-Q1 8-Bit SIPO Shift Registers

Texas Instruments SN74ACT164-Q1 8-Bit Serial-In/Parallel-Out (SIPO) Shift Registers contain an 8-bit shift register with asynchronous clear (CLR) input and AND-gated serial inputs. The gated serial inputs (A and B) permit complete control over incoming data. A low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, determining the first flip-flop's state. Provided the minimum set-up time requirements are met, the data at the serial inputs can be changed while CLK is low or high. The clocking occurs on the low-to-high-level transition of CLK. Texas Instruments SN74ACT164-Q1 devices are AEC-Q100 qualified for automotive applications.