LMK61E2BBA-SIAT

Texas Instruments
595-LMK61E2BBA-SIAT
LMK61E2BBA-SIAT

Mfr.:

Description:
Clock Generators & Support Products Ultra-Low Jitter Pro grammable Oscillator A 595-LMK61E2BBA-SIAR

ECAD Model:
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In Stock: 49

Stock:
49
Can Dispatch Immediately
On Order:
250
Expected 3/6/2026
Factory Lead Time:
6
Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 250)

Pricing (EUR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™
27,41 € 27,41 €
22,17 € 221,70 €
20,87 € 521,75 €
19,44 € 1.944,00 €
Full Reel (Order in multiples of 250)
18,75 € 4.687,50 €
18,34 € 9.170,00 €
1.000 Quote
† A MouseReel™ fee of 5,00 € will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable.

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Clock Generators & Support Products
RoHS:  
Programmable Clock Generator
1 Output
900 MHz
QFM-8
55 %
90 fs
3.465 V
3.135 V
LMK61E2
152 mA
- 40 C
+ 85 C
SMD/SMT
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Moisture Sensitive: Yes
Operating Supply Voltage: 3.3 V
Output Type: LVDS
Product Type: Clock Generators
Factory Pack Quantity: 250
Subcategory: Clock & Timer ICs
Tradename: PLLatinum
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CNHTS:
8542391090
USHTS:
8542310030
ECCN:
EAR99

LMK61E2 Ultra-Low Jitter Programmable Oscillator

Texas Instruments LMK61E2 Ultra-Low Jitter Fully Programmable Oscillator is a PLLatinum™ programmable oscillator with a fractional-N frequency synthesizer. These include an integrated VCO that generates commonly used reference clocks. The outputs can be configured as LVPECL or LVDS or HCSL. The device features self-startup from on-chip EEPROM that is factory programmed to generate 156.25MHz LVPECL output. The device registers and EEPROM settings are fully programmable in-system via the I2C serial interface. Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device provides fine and coarse frequency margining options via the I2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin testing.