LMK1D1212RHAR

Texas Instruments
595-LMK1D1212RHAR
LMK1D1212RHAR

Mfr.:

Description:
Clock Buffer 12-channel output 1. 8-V 2.5-V and 3.3- LMK1D1212RHAT

Datasheet:
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Learn more about Texas Instruments LMK1D1212RHAR

In Stock: 2.803

Stock:
2.803 Can Dispatch Immediately
Factory Lead Time:
6 Weeks Estimated factory production time for quantities greater than shown.
Long lead time reported on this product.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 2500)

Pricing (EUR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™ †
10,99 € 10,99 €
8,61 € 86,10 €
8,02 € 200,50 €
7,48 € 748,00 €
Full Reel (Order in multiples of 2500)
7,48 € 18.700,00 €
5.000 Quote
† A MouseReel™ fee of 5,00 € will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable. ↩

Alternative Packaging

Mfr. Part No.:
LMK1D1212RHAT
Packaging:
Reel, Cut Tape, MouseReel
Availability:
In Stock
Price:
12,86 €
Min:
1

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Clock Buffer
RoHS:  
12 Output
2 GHz
575 ps
LVDS
VQFN-40
HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
250 MHz
1.8 V
3.3 V
LMK1D1212
- 40 C
+ 105 C
Brand: Texas Instruments
Development Kit: LMK1D1212EVM
Duty Cycle - Max: 55 %
Mounting Style: SMD/SMT
Operating Supply Current: 65 mA
Packaging: Reel
Packaging: Cut Tape
Packaging: MouseReel
Product: Clock Buffers
Product Type: Clock Buffers
Factory Pack Quantity: 2500
Subcategory: Clock & Timer ICs
Type: LVDS Buffer
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Attributes selected: 0

Datasheet

PCN

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Compliance Codes
CNHTS:
8542399000
USHTS:
8542390090
ECCN:
EAR99
Origin Classifications
Country of Origin:
China
Assembly Country of Origin:
China
Country of Diffusion:
Germany
The country is subject to change at the time of shipment.

LMK1D121x Low Additive Jitter LVDS Clock Buffer

Texas Instruments LMK1D121x Low Additive Jitter LVDS Clock Buffer is specifically designed for driving 50Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The LMK1D1212 distributes with minimum skew one of two selectable clock inputs (IN0 and IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.

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