CDCM9102RHBT

Texas Instruments
595-CDCM9102RHBT
CDCM9102RHBT

Mfr.:

Description:
Clock Synthesizer/Jitter Cleaner Low Noise 2 Channel 100MHz Clock Gen A 5 A 595-CDCM9102RHBR

ECAD Model:
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In Stock: 415

Stock:
415 Can Dispatch Immediately
Factory Lead Time:
18 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 250)

Pricing (EUR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™
5,69 € 5,69 €
4,39 € 43,90 €
4,06 € 101,50 €
3,70 € 370,00 €
Full Reel (Order in multiples of 250)
3,12 € 780,00 €
† A MouseReel™ fee of 5,00 € will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable.

Alternative Packaging

Mfr. Part No.:
Packaging:
Reel, Cut Tape, MouseReel
Availability:
In Stock
Price:
4,83 €
Min:
1

Similar Product

Texas Instruments CDCM9102RHBR
Texas Instruments
Clock Synthesizer/Jitter Cleaner Low Noise 2 Channel 100MHz Clock Gen A 5 A 595-CDCM9102RHBT

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Clock Synthesizer/Jitter Cleaner
RoHS:  
9 Output
1.296 GHz
LVDS, LVPECL
LVCMOS, LVDS, LVPECL
VQFN-32
25 MHz
- 40 C
+ 85 C
CDCM9102
SMD/SMT
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Development Kit: CDCM9102EVM
Moisture Sensitive: Yes
Product Type: Clock Synthesizers / Jitter Cleaners
Factory Pack Quantity: 250
Subcategory: Clock & Timer ICs
Unit Weight: 72,200 mg
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TARIC:
8542399000
CNHTS:
8542399000
CAHTS:
8542390000
USHTS:
8542390090
JPHTS:
854239099
MXHTS:
8542399901
ECCN:
EAR99

CDCM9102 Two Channel 100MHz Clock Generator

Texas Instruments CDCM9102 Low Noise Two Channel 100MHz Clock Generator is designed to provide reference clocks for communications standards such as PCI Express™. CDCM9102 is easy to configure and use. This Texas Instruments clock generator provides two 100MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. A single-ended 25MHz clock output port is also provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25MHz crystal.