ADC32J44IRGZR

Texas Instruments
595-ADC32J44IRGZR
ADC32J44IRGZR

Mfr.:

Description:
Analog to Digital Converters - ADC Dual-Channel 14-Bit 125-MSPS Analog-to A A 595-ADC32J44IRGZT

Datasheet:
ECAD Model:
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Availability

Stock:
Non-Stocked
Factory Lead Time:
18 Weeks Estimated factory production time.
Minimum: 2500   Multiples: 2500
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:
This Product Ships FREE

Pricing (EUR)

Qty. Unit Price
Ext. Price
Full Reel (Order in multiples of 2500)
34,78 € 86.950,00 €

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Analog to Digital Converters - ADC
RoHS:  
ADC32J44
SMD/SMT
VQFN-48
- 40 C
+ 85 C
Reel
Brand: Texas Instruments
ENOB - Effective Number of Bits: 11.9 Bit
Features: Low Power
Moisture Sensitive: Yes
Power Consumption: 401 mW
Product Type: ADCs - Analog to Digital Converters
SFDR - Spurious Free Dynamic Range: 90 dB
SINAD - Signal to Noise and Distortion Ratio: 72.9 dB
Factory Pack Quantity: 2500
Subcategory: Data Converter ICs
Unit Weight: 138 mg
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Attributes selected: 0

Datasheet

Images

Models

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TARIC:
8542399000
CNHTS:
8542319000
CAHTS:
8542390000
USHTS:
8542390030
JPHTS:
854239099
MXHTS:
8542399999
ECCN:
3A991.c.3

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Texas Instruments ADC3xJxx High Speed Analog-to-Digital Converters (ADCs) feature the industry's lowest-power 25 to 160MSPS analog-to-digital converters. The ADC3xJxx provides flexibility and scalability with 12 and 14-bit, 2 and 4-channel. These also include JESD204B and LVDS options, ranging from 50 - 200mw per channel. The JESD204B serial interface provides board area, FPGA/ASIC pin-count and latency improvements over traditional LVDS and CMOS interfaces. TI also offers JESD204B ADCs, DACs, clock ICs and development tools that enable quick evaluation, design and implementation of designs utilizing the JESD204B interface.
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ADC32J4x 14-Bit Analogue-to-Digital Converters (ADC)

Texas Instruments ADC32J4x 14-Bit Analog-to-Digital Converters (ADCs) are a high-linearity, ultra-low power, dual-channel, 50MSPS to 160MSPS, ADC family. These devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design. The devices support JESD204B interfaces in order to reduce the number of interface lines. This also allows for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2Gbps.
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