ADC16DX370RMER

Texas Instruments
595-ADC16DX370RMER
ADC16DX370RMER

Mfr.:

Description:
Analog to Digital Converters - ADC Analog to Digital Co nverter A 595-ADC16 A 595-ADC16DX370RME25

ECAD Model:
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This product may require additional documentation to export from the United States.

Availability

Stock:
Non-Stocked
Factory Lead Time:
18 Weeks Estimated factory production time.
Minimum: 2000   Multiples: 2000
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:
This Product Ships FREE

Pricing (EUR)

Qty. Unit Price
Ext. Price
Full Reel (Order in multiples of 2000)
412,26 € 824.520,00 €

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Analog to Digital Converters - ADC
Delivery Restrictions:
 This product may require additional documentation to export from the United States.
RoHS:  
ADC16DX370
WQFN-56
JESD204B
Pipeline
2.85 V to 3.45 V
1.15 V to 1.25 V
- 40 C
+ 85 C
Reel
Brand: Texas Instruments
DNL - Differential Nonlinearity: +/- 0.9 LSB
ENOB - Effective Number of Bits: 11.25 Bit
Features: High Performance
Moisture Sensitive: Yes
Power Consumption: 1.607 W
Product Type: ADCs - Analog to Digital Converters
SFDR - Spurious Free Dynamic Range: 85 dB
SINAD - Signal to Noise and Distortion Ratio: 69.5 dB
Factory Pack Quantity: 2000
Subcategory: Data Converter ICs
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TARIC:
8542399000
CNHTS:
8542319000
CAHTS:
8542390000
USHTS:
8542390030
JPHTS:
854239099
MXHTS:
8542399999
ECCN:
3A001.a.5.a.5

ADC16DX370 Dual 16-Bit Analog-to-Digital Converter

Texas Instruments ADC16DX370 Dual 16-Bit Analog-to-Digital Converter is a monolithic dual-channel high performance analog-to-digital converter capable of converting analog input signals into 16-bit digital words with a sampling rate of 370MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance while maintaining low power consumption. The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 interface from a 56-pin, 8mm × 8mm WQFN package. A SPI is available to configure the device that is compatible with 1.2V to 3.0V logic.