ADC12QJ1600AAV

Texas Instruments
595-ADC12QJ1600AAV
ADC12QJ1600AAV

Mfr.:

Description:
Analog to Digital Converters - ADC Quad-channel 12-bit 1.6-GSPS ADC with AD ADC12QJ1600AAVT

ECAD Model:
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Availability

Stock:
Non-Stocked
Factory Lead Time:
18 Weeks Estimated factory production time.
Minimum: 168   Multiples: 168
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:
This Product Ships FREE

Pricing (EUR)

Qty. Unit Price
Ext. Price
272,19 € 45.727,92 €

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Analog to Digital Converters - ADC
Delivery Restrictions:
 This product may require additional documentation to export from the United States.
RoHS:  
ADC12QJ1600
SMD/SMT
FCBGA-144
12 bit
4 Channel
Serial
1.6 GS/s
Differential
SAR
1.8 V to 2 V
1.05 V to 1.15 V
57.4 dB
- 40 C
+ 85 C
Tray
Brand: Texas Instruments
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: Not Available
Development Kit: ADC12QJ1600EVM, TSW12QJ1600EVM
DNL - Differential Nonlinearity: 0.2 LSB
ENOB - Effective Number of Bits: 9 bits
FPBW - Full Power Bandwidth: 6 GHz
INL - Integral Nonlinearity: 1.9 LSB
Moisture Sensitive: Yes
Number of Converters: 4 Converter
Output Type: Differential
Power Consumption: 1.91 W
Product: Analog-to-Digital Converters
Product Type: ADCs - Analog to Digital Converters
Reference Type: External, Internal
SFDR - Spurious Free Dynamic Range: 64 dB
Shutdown: No Shutdown
SINAD - Signal to Noise and Distortion Ratio: 57.5 dB
Factory Pack Quantity: 168
Subcategory: Data Converter ICs
Type: Analog to Digital Converters
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USHTS:
8542390030
ECCN:
3A001.a.5.a.3

ADC12QJ1600-SP Quad Channel ADC

Texas Instruments ADC12QJ1600-SP Quad Channel Analog-to-Digital Converter (ADC) features 12-bit resolution, a high sampling rate (1.6GSPS maximum), and low power consumption, making it ideal for a variety of multi-channel communications systems. The full-power input bandwidth (-3dB) of 6GHz allows direct RF sampling of the L-band and S-band. The ADC12QJ1600-SP includes clocking features to relax system hardware requirements, such as an internal phase-locked loop (PLL) with an integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs can clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output are included for pulsed systems.