74LVC1G74GN,115

74LVC1G74 Single D-type Flip-Flop

NXP Semiconductors 74LVC1G74 Single D-type Flip-Flop is a single positive-edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (S'D) and reset (R'D) inputs, and complementary Q and Q' outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. NXP Semiconductors 74LVC1G74 Single D-type Flip-Flop is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down.