LS1012ASE7HKB

NXP Semiconductors
771-LS1012ASE7HKB
LS1012ASE7HKB

Mfr.:

Description:
Microprocessors - MPU 1012A Low Power Comm Processor

Datasheet:
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This product may require additional documentation to export from the United States.

In Stock: 60

Stock:
60 Can Dispatch Immediately
Factory Lead Time:
26 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:

Pricing (EUR)

Qty. Unit Price
Ext. Price
28,57 € 28,57 €
23,00 € 230,00 €
21,61 € 540,25 €
19,66 € 1.966,00 €
19,65 € 3.301,20 €
1.008 Quote

Product Attribute Attribute Value Select Attribute
NXP
Product Category: Microprocessors - MPU
Delivery Restrictions:
 This product may require additional documentation to export from the United States.
RoHS:  
ARM Cortex A53
1 Core
64 bit
1 GHz
VFLGA-211
32 kB
32 kB
900 mV
LS1012A
SMD/SMT
0 C
+ 105 C
Tray
Brand: NXP Semiconductors
Data RAM Size: 128 kB
Instruction Type: Floating Point
Interface Type: I2C, I2S, JTAG, SDIO, SPI, UART
L2 Cache Instruction / Data Memory: 256 kB
Memory Type: DDR3L
Moisture Sensitive: Yes
Product Type: Microprocessors - MPU
Factory Pack Quantity: 168
Subcategory: Microprocessors - MPU
Tradename: QorIQ
Watchdog Timers: Watchdog Timer
Part # Aliases: 935352628557
Unit Weight: 164,300 mg
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Attributes selected: 0

Datasheet

TARIC:
8542319000
CNHTS:
8542319091
CAHTS:
8542310000
USHTS:
8542310030
ECCN:
5A002.a.1

QorIQ Layerscape LS1012A Low Power Comm ICs

NXP QorIQ Layerscape LS1012A Low Power Communications Processor is optimized for battery-backed or USB-powered, space-constrained networking and IoT applications. The LS1012A processor integrates a single ARM Cortex-A53 core running up to 800MHz with L1 and ECC-protected L2 caches. The device incorporates the same trust architecture and software compatibility of the higher-tier QorIQ LS family devices. The LS1012A processor features 32KB of L1 instruction and data cache and 256KB of coherent L2 cache. This device features a three-lane, 6GHz multi-protocol SerDes that provides support for high-speed interfaces. Support includes up to two Gigabit Ethernet ports, a DMA-controlled PCI Express® generation 2.0 port, and one SATA 3.0 port. The LS1012A also features dual USB controllers—one supporting SuperSpeed USB 3.0 with integrated PHY, the other supporting USB 2.0 functions. Additional interfaces include QuadSPI and support for SD/MMC. This processor provides intelligent integration and extreme power efficiency in a small 9.6mm x 9.6mm package for fanless, small form factor networking and IoT applications.

Layerscape Architecture

NXP Layerscape Architecture is the underlying system architecture of the QorIQ® LS series processors. The architecture enables next-generation networks with up to 100Gb/s performance and enhanced packet processing capabilities. Design effort is simplified with a standard, open programming model and a software-aware architecture framework. This design enables customers to fully exploit the underlying hardware for maximum optimization, with the capability to easily adapt to network changes for real-time soft control over the network. A uniform hardware and software model provides the compatibility and scalability required for designing end-to-end networking equipment from home-to carrier-class products. The core-agnostic architecture incorporates the optimum core for the given application: Arm® cores or Power Architecture® cores.

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