IM2G16D3FDBG-125

Intelligent Memory
822-IM2G16D3FDBG-125
IM2G16D3FDBG-125

Mfr.:

Description:
DRAM DDR3 2Gb, 1.35V/1.5V, 128Mx16, 800MHz (1600Mbps), 0C to +95C, FBGA-96

Datasheet:
ECAD Model:
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More Information
Learn more about Intelligent Memory IM2G16D3FDBG-125

Availability

Stock:
0

You can still purchase this product for backorder.

Factory Lead Time:
8 Weeks Estimated factory production time.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:

Pricing (EUR)

Qty. Unit Price
Ext. Price
15,20 € 15,20 €
14,10 € 141,00 €
13,66 € 341,50 €
13,33 € 666,50 €
12,99 € 1.299,00 €
12,57 € 2.488,86 €
12,26 € 7.282,44 €
1.188 Quote

Product Attribute Attribute Value Select Attribute
Intelligent Memory
Product Category: DRAM
RoHS:  
SDRAM - DDR3L
2 Gbit
16 bit
800 MHz
FBGA-96
128 M x 16
20 ns
1.283 V
1.45 V
0 C
+ 95 C
IM2G16D3
Tray
Brand: Intelligent Memory
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 198
Subcategory: Memory & Data Storage
Supply Current - Max: 240 mA
Unit Weight: 166 mg
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Attributes selected: 0

Datasheet

Compliance Codes
CAHTS:
8542320020
USHTS:
8542320036
MXHTS:
8542320299
ECCN:
EAR99
Origin Classifications
Country of Origin:
Taiwan
Assembly Country of Origin:
Not available
Country of Diffusion:
Not available
The country is subject to change at the time of shipment.

Double Data Rate 3 (DDR3) DRAM

Intelligent Memory Double Data Rate 3 (DDR3) DRAM provides 1Gb to 16Gb densities for commercial and industrial applications. These ICs support Off-Chip Driver (OCD) impedance and On-Die Termination (ODT). The Intelligent Memory DDR3 DRAM features write leveling, programmable burst lengths, and CAS latency in FBGA-78 and FBGA-96 packages.

Dynamic Random Access Memory (DRAM)

Intelligent Memory Dynamic Random Access Memory (DRAM) includes a full range of JEDEC-compliant DRAMs and ECC DRAMs (SDRAM, DDR, DDR2, DDR3, DDR4, LPDDR4). From an application's point of view, these components work like a monolithic device. The DRAM devices allow for maximum levels of memory density without altering existing board layouts or designs.

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