IM2G16D2DBBG-25I

Intelligent Memory
822-IM2G16D2DBBG-25I
IM2G16D2DBBG-25I

Mfr.:

Description:
DRAM DDR2 2Gb, 1.8V, 128Mx16, 400MHz (800Mbps), -40C to +95C, FBGA-84

Datasheet:
ECAD Model:
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Learn more about Intelligent Memory IM2G16D2DBBG-25I

Availability

Stock:
0

You can still purchase this product for backorder.

On Order:
417
Expected 11/20/2026
Factory Lead Time:
26
Weeks Estimated factory production time for quantities greater than shown.
Long lead time reported on this product.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:

Pricing (EUR)

Qty. Unit Price
Ext. Price
44,32 € 44,32 €
40,96 € 409,60 €
39,64 € 991,00 €
38,65 € 1.932,50 €
37,68 € 3.768,00 €

Product Attribute Attribute Value Select Attribute
Intelligent Memory
Product Category: DRAM
RoHS:  
SDRAM - DDR2
2 Gbit
16 bit
400 MHz
FBGA-84
128 M x 16
400 ps
1.7 V
1.9 V
- 40 C
+ 95 C
IM2G16D2
Tray
Brand: Intelligent Memory
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 209
Subcategory: Memory & Data Storage
Supply Current - Max: 58 mA
Unit Weight: 194 mg
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Attributes selected: 0

Datasheet

Compliance Codes
CAHTS:
8542320020
USHTS:
8542320036
MXHTS:
8542320299
ECCN:
EAR99
Origin Classifications
Country of Origin:
China
Assembly Country of Origin:
Not available
Country of Diffusion:
Not available
The country is subject to change at the time of shipment.

Dynamic Random Access Memory (DRAM)

Intelligent Memory Dynamic Random Access Memory (DRAM) includes a full range of JEDEC-compliant DRAMs and ECC DRAMs (SDRAM, DDR, DDR2, DDR3, DDR4, LPDDR4). From an application's point of view, these components work like a monolithic device. The DRAM devices allow for maximum levels of memory density without altering existing board layouts or designs.

Double Data Rate 2 (DDR2) SDRAM

Intelligent Memory Double Data Rate (DDR2) Synchronous DRAM (SDRAM) are eight-bank devices that achieve high-speed data transfer rates. Interleaving the eight memory banks allows random access operations faster than standard DRAMs. A chip architecture prefetches multiple bits and then synchronizes the output data to a system clock. All control, address, and circuits are synchronized with the positive edge of an externally supplied clock. In a source-synchronous manner, I/Os are synchronized with a pair of bidirectional strobes. A sequential, gapless data rate is possible depending on the device's burst length, CAS latency, and speed grade.

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