IM1G16D2DDBG-25

Intelligent Memory
822-IM1G16D2DDBG-25
IM1G16D2DDBG-25

Mfr.:

Description:
DRAM DDR2 1Gb, 1.8V, 64Mx16, 400MHz (800Mbps), 0C to +95C, FBGA-84

Datasheet:
ECAD Model:
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More Information
Learn more about Intelligent Memory IM1G16D2DDBG-25

In Stock: 418

Stock:
418 Can Dispatch Immediately
Factory Lead Time:
8 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
-,-- €
Ext. Price:
-,-- €
Est. Tariff:

Pricing (EUR)

Qty. Unit Price
Ext. Price
8,78 € 8,78 €
8,17 € 81,70 €
7,91 € 197,75 €
7,73 € 386,50 €
7,54 € 754,00 €
7,29 € 1.523,61 €
6,85 € 2.863,30 €
6,68 € 6.980,60 €
2.508 Quote

Product Attribute Attribute Value Select Attribute
Intelligent Memory
Product Category: DRAM
RoHS:  
SDRAM - DDR2
1 Gbit
16 bit
400 MHz
FBGA-84
64 M x 16
400 ps
1.7 V
1.9 V
0 C
+ 95 C
IM1G16D2
Tray
Brand: Intelligent Memory
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 209
Subcategory: Memory & Data Storage
Supply Current - Max: 75 mA
Unit Weight: 192 mg
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Attributes selected: 0

Datasheet

Compliance Codes
CNHTS:
8542329010
CAHTS:
8542320020
USHTS:
8542320032
MXHTS:
8542320299
ECCN:
EAR99
Origin Classifications
Country of Origin:
Taiwan
Assembly Country of Origin:
Not available
Country of Diffusion:
Not available
The country is subject to change at the time of shipment.

Dynamic Random Access Memory (DRAM)

Intelligent Memory Dynamic Random Access Memory (DRAM) includes a full range of JEDEC-compliant DRAMs and ECC DRAMs (SDRAM, DDR, DDR2, DDR3, DDR4, LPDDR4). From an application's point of view, these components work like a monolithic device. The DRAM devices allow for maximum levels of memory density without altering existing board layouts or designs.

Double Data Rate 2 (DDR2) SDRAM

Intelligent Memory Double Data Rate (DDR2) Synchronous DRAM (SDRAM) are eight-bank devices that achieve high-speed data transfer rates. Interleaving the eight memory banks allows random access operations faster than standard DRAMs. A chip architecture prefetches multiple bits and then synchronizes the output data to a system clock. All control, address, and circuits are synchronized with the positive edge of an externally supplied clock. In a source-synchronous manner, I/Os are synchronized with a pair of bidirectional strobes. A sequential, gapless data rate is possible depending on the device's burst length, CAS latency, and speed grade.

An unexpected error has occurred.


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