SWR-MODELSIM-AE

989-SWR-MODELSIM-AE
SWR-MODELSIM-AE

Mfr.:

Description:
Development Software ModelSim Altera Ed. (RENEWAL)

Lifecycle:
Obsolete
Datasheet:
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Product Attribute Attribute Value Select Attribute
Altera
Product Category: Development Software
Delivery Restrictions:
 Mouser does not presently sell this product in your region.
RoHS:
Software
Arria, Cyclone, Stratix
Brand: Altera
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: Not Available
Description/Function: Renewal
Product Type: Development Software
Series: Quartus
Factory Pack Quantity: 1
Subcategory: Embedded Solutions
Tradename: Quartus
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Datasheet

PCN

CNHTS:
8543709990
USHTS:
4911100080
ECCN:
3D991

SoC FPGA Family

Altera SoC FPGAs integrate an Arm-based hard processor system (HPS) consisting of processors, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The devices combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. These user-customizable Arm-based SoC FPGAs are ideal for reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA. They differentiate the end product with custom hardware and software and add support for virtually any interface standard or protocol in the FPGA.

Quartus® Prime Design Software

Altera Quartus® Prime Design Software delivers improvements across the three key areas designers care about most performance, productivity, and usability. It supports the latest Agilex™ 7 and Agilex 5 FPGA and SoC families, ensuring a seamless development experience for cutting-edge applications. Coming in an upcoming release, support for the new Agilex 3 FPGAs and SoCs family and new MAX 10 FPGA package options that squeeze 485 I/Os into a 19 x 19mm2 sized package. Fast compile times allow designers to accelerate FPGA development, with larger designs benefiting from even greater reductions. Enhanced compiler optimizations also significantly reduce peak virtual memory requirements, ensuring most FPGA designs compile within 64GB of memory. 

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