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AS4C512M16D3LB-12BCNTR

Name: Alliance Memory AS4C512M16D3LB-12BCNTR
Brand: Alliance Memory
SKU: 913-4C51216D3LB12BCT
Price: 59.73 EUR
Availability: OutOfStock

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See Product Specifications

Mouser No:

913-4C51216D3LB12BCT

Mfr. No:

AS4C512M16D3LB-12BCNTR

Mfr.:

Alliance Memory

Description:

DRAM DDR3L, 8Gb, 512M X 16, 1.35V, 96-BALL FBGA, 800MHZ COMMERCIAL TEMP, T&R, B Die (MT41K512M16HA-125:A)

Datasheet:

AS4C512M16D3LB-12BCNTR Datasheet (PDF)

ECAD Model:

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More Information

Learn more about Alliance Memory AS4C512M16D3LB-12BCNTR

Availability

Stock:: Non-Stocked

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Factory Lead Time:: 20 Weeks Estimated factory production time.

Enter Quantity:

Minimum: 2000 Multiples: 2000

Unit Price:

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Ext. Price:

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Est. Tariff:

This Product Ships FREE

Pricing (EUR)

Qty.	Unit Price	Ext. Price
Full Reel (Order in multiples of 2000)
	59,73 €	119.460,00 €

Alternative Packaging

Mfr. Part No.:

AS4C512M16D3LB-12BCN

Packaging:

Tray

Availability:

In Stock

Price:

81,32 €

Min:

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM - DDR3L
Memory Size:	8 Gbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	800 MHz
Package/Case:	FBGA-96
Organisation:	512 M x 16
Access Time:	20 ns
Supply Voltage - Min:	1.283 V
Supply Voltage - Max:	1.45 V
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 95 C
Series:	AS4C512M16D3LB-12
Packaging:	Reel
Brand:	Alliance Memory
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	2000
Subcategory:	Memory & Data Storage
Supply Current - Max:	122 mA

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Datasheet

AS4C512M16D3LB-12BCNTR Datasheet (PDF)

Compliance Codes

USHTS:: 8542320036
ECCN:: EAR99

Origin Classifications

Country of Origin:: Taiwan
Assembly Country of Origin:: Taiwan
Country of Diffusion:: Taiwan

The country is subject to change at the time of shipment.

DDR3 Synchronous DRAM

Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features, and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source synchronous fashion. These Alliance Memory devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface that transfers two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Alliance Memory DDR3L SDRAM is available in various package sizes.