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AS4C32M16SC-7TIN

Name: Alliance Memory AS4C32M16SC-7TIN
Brand: Alliance Memory
SKU: 913-AS4C32M16SC-7TIN
Price: 20.29 EUR
Availability: InStock

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Mouser No:

913-AS4C32M16SC-7TIN

Mfr. No:

AS4C32M16SC-7TIN

Mfr.:

Alliance Memory

Description:

DRAM 512Mb 32Mx16 3.3V 143MHz SDRAM I-Temp

Datasheet:

AS4C32M16SC-7TIN Datasheet (PDF)

ECAD Model:

Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

More Information

Learn more about Alliance Memory AS4C32M16SC-7TIN

In Stock: 540

Stock:: 540 Can Dispatch Immediately

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Factory Lead Time:: 8 Weeks Estimated factory production time for quantities greater than shown.

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Ext. Price:

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Pricing (EUR)

Qty.	Unit Price	Ext. Price
	20,29 €	20,29 €
	18,80 €	188,00 €
	18,21 €	455,25 €
	17,76 €	888,00 €
	17,26 €	1.864,08 €
	16,58 €	3.581,28 €

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM
Memory Size:	512 Mbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	133 MHz
Package/Case:	TSOP-II-54
Organisation:	32 M x 16
Access Time:	17 ns
Supply Voltage - Min:	3 V
Supply Voltage - Max:	3.6 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Series:	AS4C32M16SC
Packaging:	Tray
Brand:	Alliance Memory
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	108
Subcategory:	Memory & Data Storage
Supply Current - Max:	60 mA

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Datasheet

AS4C32M16SC-7TIN Datasheet (PDF)

REACH Declaration (PDF)

Compliance Codes

CNHTS:: 8542329010
CAHTS:: 8542320020
USHTS:: 8542320028
MXHTS:: 8542320299
ECCN:: EAR99

Origin Classifications

Country of Origin:: Taiwan
Assembly Country of Origin:: Taiwan
Country of Diffusion:: Taiwan

The country is subject to change at the time of shipment.

AS4C SDRAM

Alliance Memory AS4C SDRAM is high-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.